--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   19:40:06 10/28/2013
-- Design Name:   
-- Module Name:   C:/Users/samsung/Desktop/CG3207/Lab3AB/Test_Mult_div.vhd
-- Project Name:  Lab3AB
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: mult_div
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY Test_Mult_div IS
END Test_Mult_div;
 
ARCHITECTURE behavior OF Test_Mult_div IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT mult_div
    PORT(
         signControl : IN  std_logic;
         divControl : IN  std_logic;
         clock : IN  std_logic;
         a : IN  std_logic_vector(31 downto 0);
         b : IN  std_logic_vector(31 downto 0);
         result : OUT  std_logic_vector(63 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal signControl : std_logic := '0';
   signal divControl : std_logic := '0';
   signal clock : std_logic := '0';
   signal a : std_logic_vector(31 downto 0) := (others => '0');
   signal b : std_logic_vector(31 downto 0) := (others => '0');

 	--Outputs
   signal result : std_logic_vector(63 downto 0);

   -- Clock period definitions
   constant clock_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: mult_div PORT MAP (
          signControl => signControl,
          divControl => divControl,
          clock => clock,
          a => a,
          b => b,
          result => result
        );

   -- Clock process definitions
   clock_process :process
   begin
		clock <= '0';
		wait for clock_period/2;
		clock <= '1';
		wait for clock_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

		signControl <= '0';
		divControl <= '0';

      a <= X"00000002";
		b <= X"0000000A";
		wait for 10 ns;
		
		wait for 100 ns;	

      a <= X"00002710";
		b <= X"00002710";
		wait for 10 ns;
		
		wait for 100 ns;	
		
		a <= X"00002710";
		b <= X"000186A0";
		wait for 10 ns;
		
		wait for 100 ns;	
		
		a <= X"000186A0";
		b <= X"000186A0";
		wait for 10 ns;
		
		wait for 100 ns;	
		
		a <= X"000F4240";
		b <= X"000F4240";
		wait for 10 ns;
		
		wait for 100 ns;	

		a <= X"00800001";
		b <= X"00800001";
		wait for 10 ns;
		
		wait for 100 ns;	
		
		a <= X"80000000";
		b <= X"80000000";
		wait for 10 ns;
		
		wait for 100 ns;	
		
		a <= X"80000000";
		b <= X"10000000";
		wait for 10 ns;
		
		wait for 100 ns;
		
      a <= X"3B9ACA00";
		b <= X"3B9ACA00";
		wait for 10 ns;

      -- insert stimulus here 

      wait;
   end process;

END;
